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least 256 Mbit to several gigabytes In such a system, per-pin bandwidth is lessl important, since many DRAM chips are required to provide the requisite capacity anyway, and these chips can be arranged in parallel to provide a wide interface-; that supplies the required bandwidth Of course, this increases the package cost of* the memory controller chip, since it has to have enough pins to access multiple DRAM chips in parallel On the other hand, product cost can be lowered by using less aggressive and less expensive circuit board technology, since each pin signals at a lower rate Detailed performance evaluation and comparison of various modem DRAM technologies can be found in two recent studies [Cuppu et al, 1999; Cuppu and*; Jacob, 2001] 3442 Memory Controller Organization Memory controllers serve as the interface between a system's processor bus, which communicates reads and writes issued by the processor, and the standard DRAM command interface, which, expects a tighdy specified sequence of commands for supplying row addresses, column addresses, and read or write commands to each DRAM chip There are many alternatives for arranging the mapping between the physical addresses provided by the processor and the DRAM addresses needed to access the actual storagelocations Furthermore, there are various optimizations that can be applied within the; memory controller to improve read performance and increase spatial locality in the DRAM reference stream The net effect is that the design of the memory controller can substantially impact sustainable memory bandwidth and the observed latency of j memory references The following sections discuss some of these issues in detail M e m o r y Module Organization The desired memory capacity for a system < determines the total number of DRAM chips needed to provide that capacity In practice, most systems are designed to support a range of capacities to enable use of several generations of memory chips and to allow for future expansion from an initial* configuration However, for simplicity we will assume a fixed capacity only, resulting in a fixed number of DRAM chips in the memory subsystem Figure 39 illustrates four possible organizations for four DRAM chips in a system, as determined by J two fundamental attributes: serial vs parallel and interleaved vs non-interleaved In the top left case, the DRAM chips all share the same address, command, and data lines, but only a single chip is active at a time when it is selected via its chip select'i (CS) control line In this case, the number of pins required in the controller is minimized, since all pins except for the CS control lines are shared However, data bandwidth is limited by the data bus width of each DRAM chip DRAM chips have 2 , 4 , 8, or 16 data lines typically 4 or 8 in current-generation chips with a price premium charged for wider interfaces In this organization, transaction bandwidth is' restricted to one concurrent command, since the address and command lines are shared across all chips The top right case in Figure 39 shows a parallel organization, in which all chips are active for all commands (hence, no chip selects), and the n-bit data busses from each chip are concatenated to form a 4n-bit interface This configuration provides much better data bandwidth, but at a higher memory controller cost due to the private data bus pins for each DRAM chip It provides no increase in transaction bandwidth, since the address and command lines are still shared The bottom left shows an interleaved (or banked) organization where half the DRAM chips are connected to one set of chip select, address, command, and data busses, while the other half is connected to a second set This organization provides twice the data bandwidth, and also twice the transaction bandwidth, since each interleaved bank can now operate independently, at the cost of twice as many address and command pins The final configuration, on the bottom right, combines the parallel and interleaved organizations, providing twice the transaction bandwidth through interleaving, and four times the data bandwidth through two 2/i-bit wide data busses Of course, this final configuration requires the highest cost and largest number of pins in the'memory controller There are other possible combinations of these techniques (for example, a semi-parallel scheme where only half instead of all DRAM chips are in parallel, and chip selects are still used to select which half drives the 2/i-bit wide data bus) In all these combinations, however, the linear physical address presented by the processor needs to be translated to an n-tuple that describes the actual physical location of the memory location being addressed Table 33 summarizes the contents of the DRAM address n-tuple for several approaches for organizing memory modules Linear physical addresses are mapped to these n-tuples by selecting appropriately sized subsets of bits from the physical address to form each element. rdlc pdf 417 PDF417 Barcode Creating Library for RDLC Reports | Generate ...
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